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<div class="title">xtft_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:ga6da9efdd6a18854c2994f2260e2b1482"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#ga6da9efdd6a18854c2994f2260e2b1482">XTFT_CHAR_WIDTH</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga6da9efdd6a18854c2994f2260e2b1482"><td class="mdescLeft">&#160;</td><td class="mdescRight">Dimension Definitions.  <a href="group__tft__v5__0.html#ga6da9efdd6a18854c2994f2260e2b1482">More...</a><br /></td></tr>
<tr class="separator:ga6da9efdd6a18854c2994f2260e2b1482"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e190b26de7e75aa55a59319c573a227"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#ga1e190b26de7e75aa55a59319c573a227">XTFT_CHAR_HEIGHT</a>&#160;&#160;&#160;12</td></tr>
<tr class="memdesc:ga1e190b26de7e75aa55a59319c573a227"><td class="mdescLeft">&#160;</td><td class="mdescRight">Character height.  <a href="group__tft__v5__0.html#ga1e190b26de7e75aa55a59319c573a227">More...</a><br /></td></tr>
<tr class="separator:ga1e190b26de7e75aa55a59319c573a227"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8cdf302af29f0563c0079c0cbfb6abff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#ga8cdf302af29f0563c0079c0cbfb6abff">XTFT_DISPLAY_WIDTH</a>&#160;&#160;&#160;640</td></tr>
<tr class="memdesc:ga8cdf302af29f0563c0079c0cbfb6abff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Width of the screen.  <a href="group__tft__v5__0.html#ga8cdf302af29f0563c0079c0cbfb6abff">More...</a><br /></td></tr>
<tr class="separator:ga8cdf302af29f0563c0079c0cbfb6abff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d391c05df971dfe77189be6daf57521"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#ga3d391c05df971dfe77189be6daf57521">XTFT_DISPLAY_HEIGHT</a>&#160;&#160;&#160;480</td></tr>
<tr class="memdesc:ga3d391c05df971dfe77189be6daf57521"><td class="mdescLeft">&#160;</td><td class="mdescRight">Height of the screen.  <a href="group__tft__v5__0.html#ga3d391c05df971dfe77189be6daf57521">More...</a><br /></td></tr>
<tr class="separator:ga3d391c05df971dfe77189be6daf57521"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d27aca52ce921aee61dab5870700c5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#ga4d27aca52ce921aee61dab5870700c5b">XTFT_DISPLAY_BUFFER_WIDTH</a>&#160;&#160;&#160;1024</td></tr>
<tr class="memdesc:ga4d27aca52ce921aee61dab5870700c5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer width of a line.  <a href="group__tft__v5__0.html#ga4d27aca52ce921aee61dab5870700c5b">More...</a><br /></td></tr>
<tr class="separator:ga4d27aca52ce921aee61dab5870700c5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d988ed9da8b7e1ff66b120a13772d82"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#ga2d988ed9da8b7e1ff66b120a13772d82">XTFT_DCR_REG_SHIFT</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga2d988ed9da8b7e1ff66b120a13772d82"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reg Shift for DCR Access.  <a href="group__tft__v5__0.html#ga2d988ed9da8b7e1ff66b120a13772d82">More...</a><br /></td></tr>
<tr class="separator:ga2d988ed9da8b7e1ff66b120a13772d82"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TFT Register offsets</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The following definitions provide access to each of the registers of the TFT device. </p>
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<tr class="memitem:ga3f2dda8ffdcd2d04e9307cc7f3edaa11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#ga3f2dda8ffdcd2d04e9307cc7f3edaa11">XTFT_AR_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga3f2dda8ffdcd2d04e9307cc7f3edaa11"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address Reg (Video memory) Offset.  <a href="group__tft__v5__0.html#ga3f2dda8ffdcd2d04e9307cc7f3edaa11">More...</a><br /></td></tr>
<tr class="separator:ga3f2dda8ffdcd2d04e9307cc7f3edaa11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5fdc2c6fd8a7dae841feb936a043dd58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#ga5fdc2c6fd8a7dae841feb936a043dd58">XTFT_CR_OFFSET</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga5fdc2c6fd8a7dae841feb936a043dd58"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register Offset.  <a href="group__tft__v5__0.html#ga5fdc2c6fd8a7dae841feb936a043dd58">More...</a><br /></td></tr>
<tr class="separator:ga5fdc2c6fd8a7dae841feb936a043dd58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6fec872a11e74e007882df480ef9d951"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#ga6fec872a11e74e007882df480ef9d951">XTFT_IESR_OFFSET</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga6fec872a11e74e007882df480ef9d951"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable and Status Reg Offset.  <a href="group__tft__v5__0.html#ga6fec872a11e74e007882df480ef9d951">More...</a><br /></td></tr>
<tr class="separator:ga6fec872a11e74e007882df480ef9d951"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad0b65c05fe82f1493e865d70878d5773"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#gad0b65c05fe82f1493e865d70878d5773">XTFT_AR_LSB_OFFSET</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:gad0b65c05fe82f1493e865d70878d5773"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address Reg LSB (Video memory) Offset.  <a href="group__tft__v5__0.html#gad0b65c05fe82f1493e865d70878d5773">More...</a><br /></td></tr>
<tr class="separator:gad0b65c05fe82f1493e865d70878d5773"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga585665d41b80da57013a246faaf7869e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#ga585665d41b80da57013a246faaf7869e">XTFT_AR_MSB_OFFSET</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:ga585665d41b80da57013a246faaf7869e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address Reg MSB (Video memory) Offset.  <a href="group__tft__v5__0.html#ga585665d41b80da57013a246faaf7869e">More...</a><br /></td></tr>
<tr class="separator:ga585665d41b80da57013a246faaf7869e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TFT Control Register (CR) mask(s)</div></td></tr>
<tr class="memitem:ga3069ee03357025e835743cbe81b7fd94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#ga3069ee03357025e835743cbe81b7fd94">XTFT_CR_TDE_MASK</a>&#160;&#160;&#160;0x01</td></tr>
<tr class="memdesc:ga3069ee03357025e835743cbe81b7fd94"><td class="mdescLeft">&#160;</td><td class="mdescRight">TFT Display Enable Bit Mask.  <a href="group__tft__v5__0.html#ga3069ee03357025e835743cbe81b7fd94">More...</a><br /></td></tr>
<tr class="separator:ga3069ee03357025e835743cbe81b7fd94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaccac2b2d2b56aed3798bd781ba5775a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#gaccac2b2d2b56aed3798bd781ba5775a5">XTFT_CR_DPS_MASK</a>&#160;&#160;&#160;0x02</td></tr>
<tr class="memdesc:gaccac2b2d2b56aed3798bd781ba5775a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">TFT Display Scan Control Bit Mask.  <a href="group__tft__v5__0.html#gaccac2b2d2b56aed3798bd781ba5775a5">More...</a><br /></td></tr>
<tr class="separator:gaccac2b2d2b56aed3798bd781ba5775a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TFT Interrupt Enable and Status Register (IESR) mask(s)</div></td></tr>
<tr class="memitem:gafcc9028848f7ab88a9461c53a5c64bf0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#gafcc9028848f7ab88a9461c53a5c64bf0">XTFT_IESR_VADDRLATCH_STATUS_MASK</a>&#160;&#160;&#160;0x01</td></tr>
<tr class="memdesc:gafcc9028848f7ab88a9461c53a5c64bf0"><td class="mdescLeft">&#160;</td><td class="mdescRight">TFT Video Address Latch Status Bit Mask.  <a href="group__tft__v5__0.html#gafcc9028848f7ab88a9461c53a5c64bf0">More...</a><br /></td></tr>
<tr class="separator:gafcc9028848f7ab88a9461c53a5c64bf0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9e75abb8c7b5263ebabb683ce1ee2b8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tft__v5__0.html#ga9e75abb8c7b5263ebabb683ce1ee2b8f">XTFT_IESR_IE_MASK</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:ga9e75abb8c7b5263ebabb683ce1ee2b8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">TFT Interrupt Enable Mask.  <a href="group__tft__v5__0.html#ga9e75abb8c7b5263ebabb683ce1ee2b8f">More...</a><br /></td></tr>
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